The impact of strain engineering on hole mobility of In(x)Ga(1-x)As channels for III-V pMOSFET

Whilst the high electron mobility of compound semiconductors makes them attractive for beyond 22 nm CMOS, a key challenge in implementing III-V materials is their modest hole mobility. Addressing this issue motivates an investigation of the impact of strain to optimize the hole transport properties of III-V MOSFET channel materials. In this work, the researchers describe the dependence of hole mobility on the bi-axial compressive strain of InxGa1-xAs layers with indium concentrations in the range 53%-85%. The vertical architecture of the material structure of this study resembles a III-V high mobility transistor where the dopant is spatially separated from the device channel. Mobility and channel carrier concentration were determined using Hall effect measurements. While the 53% In-content (0% strain) structures demonstrated modest mobilities of 60-70 cm2/Vs, the strained structures exhibited superior transport with the 85% In-content (2.1% strain) channel demonstrating mobilities of 427-433 cm2/Vs with sheet hole densities of 1.33e12 - 1.6e12 cm-2 depending on the doping level used. To their knowledge, the room temperature mobility of the 2.1% strained structures are the highest ever reported for an InxGa1-xAs channel

Low noise high performance 50nm T-gate metamorphic HEMT with cut-off frequency f_T of 440 GHz for millimeterwave imaging receivers applications

The 50 nm m-HEMT exhibits extremely high f<sub>T</sub>, of 440GHz, low F<sub>min</sub> of 0.7 dB, associated gain of 13 dB at 26 GHz with an exceptionally high Id of 200 mA/mm and gm of 950 ms/mm at low noise biased point

Fabrication of submicron planar Gunn diode

We present, for the first time, the fabrication process for a submicron planar Gunn diode in In<sub>0.53</sub>Ga<sub>0.47</sub>As on an InP substrate operating at 265 GHz. A novel two stage lift off method has been developed to achieve a submicron gaps between contacts down to 135 nm with widths up to 120 μm

Semiconductor device for generating an oscillating voltage

A semiconductor device which displays an oscillating voltage due to the creation of charge domains which includes a plurality of semiconductor layers and at least two electrodes spaced from one another in the direction of the layers, an upper of which has a composition and/or dimensions predetermined so that a charge therein balances a depletion from a surface charge of the upper layer on application of a potential difference across said electrodes. The electrodes may be in contact solely with the upper layer. A method of manufacturing the device is also provided

50-nm T-gate metamorphic GaAs HEMTs with f_T of 440 GHz and noise figure of 0.7 dB at 26 GHz

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies

A planar Gunn diode operating above 100 GHz

We show the experimental realization of a 108-GHz planar Gunn diode structure fabricated in GaAs/AlGaAs. There is a considerable interest in such devices since they lend themselves to integration into millimeter-wave and terahertz integrated circuits. The material used was grown by molecular beam epitaxy, and devices were made using electron beam lithography. Since the frequency of oscillation is defined by the lithographically controlled anode-cathode distance, the technology shows great promise in fabricating single chip terahertz sources

Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga<sub>2</sub>O<sub>3</sub> or a stack of Ga<sub>2</sub>O<sub>3</sub> and Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub>. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si delta-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> is included in a stack with 1 nm of Ga<sub>2</sub>O<sub>3</sub> at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ~3 V. However, the inclusion of Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in the gate insulator introduces many oxide states (≤4.70Ã�Â�10<sup>12</sup> cm<sup>âÂ�Â�2</sup>). Transmission electron microscope images of the interface region show that the growth of a Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer on Ga<sub>2</sub>O<sub>3</sub> disturbs the well ordered Ga<sub>2</sub>O<sub>3</sub>/GaAs interface. We therefore conclude that while including Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in a dielectric stack with Ga<sub>2</sub>O<sub>3</sub> is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga<sub>2</sub>O<sub>3</sub>/GaAs interface and near interface region by introducing roughness and a large number of defect states

Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

No abstract available

180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

Abstract: Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions

SiGe p-channel MOSFETs with tungsten gate

A self-aligned SiGe p-channel MOSFET tungsten gate process with 0.1 μm resolution is demonstrated. Interface charge densities of MOS capacitors realised with the low pressure sputtered tungsten process are comparable with thermally evaporated aluminium gate technologies (5×1010cm-2 and 2×1011 cm -2 for W and Al, respectively). Initial results from 1 μm gate length SiGe p-channel MOSFETs using the tungsten-based process show devices with a transconductance of 33 mS/mm and effective channel mobility of 190 cm